1. Field of the Invention
The present invention relates to a device and a method for debugging an electronic circuit described by a program written in a hardware description language or HDL.
2. Discussion of the Related Art
The HDL language is a programming language which has been developed and optimized for the design and the modeling of electronic circuits since it enables accurately describing the behavior of electronic circuits. It is, for example, the VHDL language (for VHSIC Hardware Description Language, with VHSIC standing for Very High Speed Integrated-Circuit), or the Verilog language.
Examples of electronic circuits formed based on HDL programs are Field Programmable Gate Array (FPGA) circuits or Application Specific Integrated circuits, or ASIC. More specifically, an FPGA circuit comprises electronic gates preimplanted on a circuit according to a given topology. In the initial state, these gates are not interconnected. To form an electronic circuit implementing specific functions based on an FPGA circuit, it is enough to create certain connections (which can be obtained by the turning-on of MOS transistors) between certain electronic gates of the FPGA to obtain the desired functions. For this purpose, a RAM in which configuration data (bitstream) especially representing circuit connections are stored may be used. The bitstream data are obtained from the HDL program describing the electronic circuit.
During the complete design process of an electronic circuit, it is necessary to provide a debugging step which comprises the error detection, diagnosis and correction, during the electronic circuit operation. For an electronic circuit designed based on an HDL program, an error correction may correspond to a modification of the HDL program describing the electronic circuit.
There currently mainly exist two types of methods for debugging an electronic circuit obtained from an HDL program.
The first method consists of using a logic analyzer. It may for example be the logic analyzer sold by Altera Company under trade name Signal TAP. A logic analyzer enables modifying the initial HDL program describing an electronic circuit to obtain a modified HDL program which describes the same electronic circuit with additional circuits which generally have no influence upon the behavior of the electronic circuit and which implement specific functions useful to debug the electronic circuit. An additional circuit may perform logic operations on given signals used by the electronic circuit and provide an alert signal when a logic condition is fulfilled, check the values of several signals in parallel, etc. The debugging of an FPGA circuit programmed from the initial HDL program is carried out by programming the FPGA circuit with the modified HDL program. The modified FPGA circuit is then operated in real time in its normal operation environment, and the logic analyzer is used to collect the different signals provided by the additional circuits added to the electronic circuit described by the initial HDL program.
However, a logic analyzer only provides a timing diagram of the signals provided by the additional circuit during the operation of the electronic circuit. A subsequent analysis of such signals is necessary to determine, in the case of the detection of an in-service error, whether such an error is due to a wrong design of the initial HDL description program and, if such is the case, to which part of the program the error having occurred is associated. Such an analysis can be excessively complex, all the more if the electronic circuit itself is complex.
The second method corresponds to a direct debugging of the HDL program. Such a debugging method may be implemented by mean of the debugger sold by Synplicity Company under trade name Identify. Such a debugger enables inserting watchpoints at the level of certain parts of an initial HDL program describing an electronic circuit and providing a modified HDL program from which an FPGA circuit, for example, is programmed. Upon operation of the modified FPGA circuit thus programmed, the debugger exchanges signals with the FPGA circuit and can indicate to a user whether the parts of the initial HDL program marked with watchpoints have been executed during the operation of the FPGA circuit. The debugger can also indicate the value of signals used by the initial HDL program at the time when the marked parts of the initial HDL program are executed. If errors occur during the operation of the FPGA circuit, the user can locate the parts of the initial HDL program at the level of which the errors have occurred.
However, such a debugger, being purely code-oriented, does not enable building complex verification scenarios based on the values of the signals used by the FPGA circuit. The absence of a tool of logic analyzer type can make the detection of certain errors upon operation of the FPGA circuit or the determination of the origin of certain detected errors difficult.